To improve the operating speed of field effect transistors (FETs), and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3-D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
The fabrication of FinFET ICs, however, encounters some processing issues. FIG. 1 illustrates, in cross section, a portion of a FinFET IC 10 of the prior art taken along an X-X′ and a Z-Z′ axis. FIG. 2 shows the relationship of the X-X′ and Z-Z′ axis to each other with respect to the FinFET IC 10. In FIG. 1, FinFET IC 10 is covered by an interlayer dielectric layer 40 while, for ease of illustration, in FIG. 2 it is not and only two fins 14 are shown. Referring to FIG. 1, FinFET IC 10 is fabricated in and on a bulk semiconductor substrate 12 from which a plurality of fins 14 have been etched. A local isolation oxide 16 is disposed between the fins 14 and has a height, as indicated by double-headed arrow 18, as measured from the semiconductor substrate 12 that is less than a height, as indicated by double-headed arrow 20, of the fins 14 as measured from the semiconductor substrate. One challenge is the formation of the local isolation layer 16 between the fins 14 that enables a uniform fin height, as indicated by double-headed arrow 22, between a top surface of the local isolation layer 16 and a top surface of the fins 14 after all fin etch, local isolation, deep trench isolation, implantation patterning, and spacer formation processes are performed before epitaxial formation. A non-uniform fin height results in non-uniform epitaxial growth of silicon-comprising material on the fins before formation of contacts 34. This non-uniform epitaxial growth results in non-uniform contact resistance between the contacts and the fins. Another challenge is to control the fin height 22 underlying a gate stack 36. Particularly during replacement gate flow where dummy oxide is removed from the gate by a diluted hydrofluoric acid wet process, the local oxide isolation could be etched as well as result in non-uniform FIN height. A non-uniform fin height underlying the gate stack 36 results in non-uniform channel widths. Yet a further challenge is control of epitaxial growth on the fins 14 so that lateral epitaxial growth does not cause shorts between adjacent active regions 30 and 32. While deep and wide shallow trench isolation regions 24 may prevent such lateral growth, they do so at the cost of valuable chip real estate.
Accordingly, it is desirable to provide methods for fabricating FinFET integrated circuits that provide for uniform fin height. In addition, it is desirable to provide methods for fabricating FinFET integrated circuits that control epitaxial growth on the fins so that lateral epitaxial growth between active regions does not result in shorts between adjacent devices. It is also desirable to provide FinFET integrated circuits formed from such methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.